1. Interrupt signals from PCI devices

    • PCI devices can request service using one of four sideband interrupt pins:
      • INTA#, INTB#, INTC#, INTD#.

  2. Legacy single-CPU systems

    • The interrupt controller collects the device interrupt.
    • Then it asserts the INTR pin to the CPU.
    • The CPU must figure out which device caused the interrupt and then handle it.
    • This process took several bus cycles and was inefficient.

  3. Multi-CPU systems and APIC

    • The old single-wire INTR line wasn’t enough for multiple CPUs.
    • APIC (Advanced Programmable Interrupt Controller) improved this:
      • Instead of pulling one CPU’s INTR pin, the APIC sends a message to one or more CPUs.
    • This allows smarter interrupt distribution (load balancing between CPUs).

  4. Still some inefficiency

    • APIC is better, but the CPU still needs to:
      • Identify the source device.
      • Execute the Interrupt Service Routine (ISR).